Microprocessors and Computer Architecture

Microprocessors and Computer Architecture

Microprocessor 8085

It is 8 bit microprocessor. It contains arithmetic and logic units. It contains register as:

PC: It holds 16 bit next instruction address.

SP: It holds 16 bit address or temporary data.

B, C, D, E, H and L are general purpose register. They are 8 bit register and can be paired to use as 16 bit register.

Instruction Register: 8 bit instruction which is being decoded.

Accumulator: It is mostly used register for arithmetic and logic operation.

Flag register: Carry, Sign, Zero, and Parity. Sign=1 if negative result. Zero=1 if result is zero. Carry=1 if overflow. Parity=1 if even no. of 1’s. There is also auxiliary carry which is used internally.

In construction of 8085, there are 16 address lines and 8 data lines.

In control lines: IO/M (bar), INTR, RST 5.5, 6.5, 7.5  

IO operation takes place if 1. Memory operation takes place if 0.

In address lines: 16 lines

In data lines: 8 lines

Power pin: Vcc

Ground pin: 0

ALE: It is used to de-multiplex address or data.

Reset in/out: Reset microprocessor if Reset in.. Reset other peripherals if reset out.

Interrupts:

Hardware interrupt

Trap- Top priority, non-mask able interrupt .. It means interrupt can’t be ignored.

RST  - Mask able vectored interrupt. It can be ignored or can be disabled by software. Vectored interrupt means can be jumped to appropriate location.

INTR- It is general purpose interrupt

Software interrupt

RST 0 to 7 ( used to call subroutine0

8086

16 bit data bus.

20 bit address bus

16 bit registers, segmented architecture

Registers types:

a.     General purpose register

AX, BX, CX, DX – It can be split into AH, AL

b.    Segment

          CS, DS, ES, SS- Code segment, Data segment, Stack Segment, Extra Segment

c.     Index and Pointer

Register for memory addressing and stack.

d.    Instruction

Holds the offset value of next instruction address

e.     Flag register

Holds status flag

Memory Segmentation:

Memory is segmented as above segment.

There is available of minimum and maximum mode for single processor or multiprocessor. Pipelining is available i.e fetch, decode and execute operation can be overlapped.

Addition of two numbers:

MOV AX, 2000H

MOV BX, 3000H

Add AX, BX

8085 programming and interfacing

In interfacing:

Memory interfacing;; Processor is connected to RAM using address data and control lines.

IO interfacing: Connecting external devices using IN/OUT instructions. I/O mapped or memory mapped.

Peripheral Interfacing: Using 8255 for advanced control of IO devices.

Instruction set, instruction format and addressing modes

There are number of instructions supported by microprocessor. Instruction are found for arithmetic, logic operation and control operation.

Instruction format can be 3 address, 2 address, 1 address and zero address instruction types.

Similarly, instruction contains mnemonics and operand. There are variety of addressing modes. Some are register based and some are memory based. They also can be direct or indirect too.

Interrupt system in microprocessor

There are hardware and software interrupts. In 8085 hardware interrupt are maskable such as RST 7.5, 6.5 and 5.5, non-maskable such as TRAP which can’t be ignored and general purpose interrupt such as INTR.

In software interrupt there is interrupt called from program instructions such as from RST 0 to 7.

Similarly, in 8086 there are also hardware and software interrupts. Hardware interrupt are like NMI (non-maskable) and INTR (maskable interrupt). And, software interrupt are like INT.

In addition to 8085, there are divide by zero interrupt available in 8086 which is internally generated interrupt.

Computer organization and architecture.

Computer architecture is about what and organization is about how. Does multiply instruction is available? It is architecture. And how that multiply instruction is achieved is addition or directly multiplication that is organization.

Control signals are also example for computer organization.

Similarly, types of instruction, number of bits by primitive data types are examples of computer architecture.

Instruction cycle, machine cycle and execution of an instruction.

Instruction cycle means fetch of instruction, decode and execute it. Interrupt can be optional.

Machine cycle is a part of instruction cycle where data are fetched between cpu, memory and i/o . Generally it doesn’t cover decoding which is a part of internal CPU works.

Execution of instruction in overall is fetch, decode and execute of instruction.

CPU structure and function, Arithmetic and Logic Unit, Representation of

data, Arithmetic operations

Structure of CPU is ALU, CU and Registers.

Function of a CPU is Data Movement, Data Storage, Data Processing and Control Signals.

ALU is circuit which contains arithmetic and logical units.

Representation of data:…

Arithmetic Operations: Adding, Subtracting are few operations in CPU.

Control Unit:

In computer, there can be hardwired or microprogrammed control unit. It is the brain of CPU. It generates control signals within for CPU or for outside CPU. Control unit takes instruction from instruction register (IR) and decode it and perform necessary operation based on whether it hardwired or microprogrammed CU.

In hardwired CU, which is faster than microprogrammed CU. Circuit is developed and it is not flexible enough for changing.

In microprogrammed CU, we have control memory which stores micro-instruction for each instruction. These contains atomic operations. Address sequencing is a component used for sub-routine of each instruction to decode. Since, the operations of an instruction is storing in computer memory it is flexible enough to change.  

Memory Devices, Classification and Hierarchies

We have different types of memory component used in Computing system. Register and L1 cache are within microprocessor. L2, L3 are near to microprocessor. Main memory are connected to cache. CPU communicate with Primary memory. These discussed memories are volatile in nature. If power is cutoff the data will be lost. However, these memory access time is fast than secondary memories (such as HDD, SDD, magnetic tapes, disks).

Classification of memory based on near to microprocessor, based on access time, based on accessing mechanism, based on storage capacity, based on response time, based on cost.

Cache Memory and Cache Mapping, Multi-level Cache Memory

Cache Memory stand between RAM and processor. The PC provides address of instruction to look if it is available in Cache then CPU reads the instruction from cache (It is called as cache Hit), if not available on cache then we call this as Cache Miss. If cache miss occurs then block of that address is copied to cache and CPU read from it.

Least Recently Used (LRU), First In First Out and Random replacement are the  and other are the mechanism in copying the data to Cache.

For cache, we have three different mechanisms to copy a block of words into cache memory from main memory.

Suppose, I have 4GB main memory. I have 128 MB cache memory.. I have block size of 16KB.

Main memory have 2*32 lines.

Block has lines of 2*14 lines.

Total cache lines 2*(7+10+10) = 2*27 lines

 For direct mapping

Now, for same problem for associative mapping.

Now, same problem for 2 lines for 1 set in set-associative mapping is:

Von Neumann and Harvard architecture

Von Neumann uses only one memory for both data as well as instructions. So, just one set of system bus for address, data and control are used to make connection between CPU and memory.

In Harvard architecture, there are two memories for data and instructions. So it has two sets of system buses. Memories are called instruction memory and data memory.

In real time systems, we often find Harvard architecture. In Harvard architecture, OS resides in instruction memory.

I/O organization: I/O programming, Memory mapped I/O, basic interrupt system, DMA

Processor is very fast in comparison to I/O. Also, processor and i/o has difference in data length, performance. So, we require I/O module to take care of it. It is connected with control bus to send/receive control signals. There are three mechanism in I/O operation: I/O programming: Here CPU continuously senses I/O for to complete operation. But in Interrupt I/O it provides control signal to I/O and performs CPU works in between then after I/O module ready then CPU do I/O works. In DMA, the system bus explicitly is provided to I/O and memory for data transfer.  There is DMA controller to do this task. Burst mode and cycle stealing are two different modes used in DMA. Burst mode has exclusive rights. But cycle stealing doesn’t have it CPU can steal the use of system bus.

Pipelining:

The concept of pipelining is simultaneously executing the sub-cycles of multiple instruction on different segments of registers.

For example: for sum = (Ai+Bi)*Ci

There are three hazards: structure, data hazard and control hazard. Structure hazard occur when both stages require same resources or resource conflict. Data hazard occur when some stage of pipeline require data from previous stage. Control hazard occur when branching and jump is required.